The present invention relates to a CMOS device, and more specifically to a CMOS device improved in withstanding latch-up.
In the structure of a CMOS, there are formed parasitic pnp and npn transistors which tend to interact and cause latch-up.
FIGS. 11 and 12 show one conventional CMOS device (U.S. Pat. No. 4,209,713, or Denshi-Tsushin-Gakkai-Ronbunshi, '78/2 vol. J61-CN02).
An n-channel MOSFET (nMOS) 7 is formed in a p well 2 which is formed in a main surface of an n-type silicon substrate 1, and a p-channel MOSFET (pMOS) 13 is formed directly in the n substrate 1. The nMOS 7 is constituted by a pair of an n.sup.+ source region 3 and an n.sup.+ drain region 4 which are both formed in the p well 2, and a gate electrode 5 formed on a gate insulating layer (not shown). A well contact region 6 of the p.sup.+ type is formed to connect together the source region 3 of the nMOS 7 and the well region 2 which serves as a substrate region of the nMOS 7. The pMOS 13 is constituted by a pair of a p.sup.+ source region 8 and a p.sup.+ drain region 9 which are both formed directly in the n substrate 1, and a gate electrode 11 formed on a gate insulating layer (not shown). A substrate contact region 12 of the n.sup.+ type is formed to connect together the source region 8 of the pMOS 13 and the substrate 1 which serves as a substrate region of the pMOS 13.
The nMOS 7 and pMOS 13 are interconnected to form a CMOS inverter. The gate electrodes 5 and 11 of both devices 7 and 13 are connected together and connected to an input terminal 14. The drain regions 4 and 9 are connected together, and connected to an output terminal 15. A supply terminal 16 of a supply voltage Vdd is connected to the source region 8 of the pMOS 13, and a low potential terminal 17 of a potential Vss is connected to the source region 3 of the nMOS 7.
In the CMOS device having such a structure, there are formed parasitic pnp transistors Q.sub.1 and Q.sub.3, and parasitic npn transistors Q.sub.2 and Q.sub.4, as shown in FIGS. 11 and 12. These parasitic bipolar transistors Q.sub.1 -Q.sub.4 are interconnected, and form a pnpn thyristor structure.
In FIG. 12, Rn.sub.1 is a base resistance of the transistor Q.sub.1, Rn.sub.3 is a base resistance of the transistor Q.sub.3, and Rp is a base resistance of the transistor Q.sub.4.
When a positive surge voltage equal to or greater than the supply voltage Vdd enters through the output terminal 15, the CMOS device falls into latch-up in the following manner. This surge voltage causes a base current Ib.sub.1 to flow between the base and emitter of the transistor Q.sub.1, and accordingly a collector current Ic.sub.1 =Ib.sub.1 .times.Hfe.sub.1 (where Hfe.sub.1 is the current gain of the transistor Q.sub.1) flows through the base resistance Rp into the low potential terminal 17.
When the voltage drop developed across the base resistance Rp by the collector current Ic.sub.1 becomes equal to or greater than a base threshold voltage Vbth.sub.4 (Ic.sub.1 .times.Rp.gtoreq.0.6 V), then a base current Ib.sub.4 flows into the transistor Q.sub.4, which accordingly draws in a collector current Ic.sub.4 =Ib.sub.4 .times.Hfe.sub.4 (where Hfe.sub.4 is the current gain of the transistor Q.sub.4) from the supply terminal 16 through the base resistance Rn.sub.3 of the transistor Q.sub.3.
This collector current Ic.sub.4 generates a voltage drop Ic.sub.4 .times.Rn.sub.3 across the resistance Rn.sub.3. When this voltage drop becomes equal to or greater than a base threshold voltage Vbth.sub.3 (approximately equal to 0.6 V) of the transistor Q.sub.3, then a current Ib.sub.3 flows through the base of the transistor Q.sub.3, and the transistor Q.sub.3 turns on. Accordingly, a collector current Ic.sub.3 =Ib.sub.3 .times.Hfe.sub.3 (where Hfe.sub.3 is the current gain of the transistor Q.sub.3) flows into the transistor Q.sub.4 and its base resistance Rp.
In this way, both the pnp transistor Q.sub.3 and the npn transistor Q.sub.4 are turned on, and the pnpn thyristor structure formed by both transistors Q.sub.3 and Q.sub.4 is brought into the latch-up state, which persists until the power supply is cut off.
A negative surge voltage equal to or lower than the low potential Vss also triggers latch-up when it is applied to the output terminal 15. In this case, a base current Ib.sub.2 is caused to flow in the npn transistor Q.sub.2, and accordingly, a collector current Ic.sub.2 flows into the transistor Q.sub.2 through the base resistance Rn.sub.3 of the transistor Q.sub.3. This collector current Ic.sub.2 develops a voltage drop Ic.sub.2 .times.Rn.sub.3 across the resistance Rn.sub.3. When this voltage drop becomes equal to or greater than the base threshold voltage Vbth.sub.3 of the transistor Q.sub.3, the transistor Q.sub.3 is turned on, and the collector current Ic.sub.3 flows through the base resistance Rp of the transistor Q.sub.4. Therefore, the transistor Q.sub.4 is also turned on when Ic.sub.3 .times.Rp becomes equal to or greater than Vbth.sub.4. In this way, the thyristor operation causes latch-up again.
Latch-up is very serious. Latch-up disables the CMOS from functioning properly. Furthermore, an excessive current flowing between the supply terminal 16 and the low potential terminal 17 due to latch-up damages the device when the power dissipation exceeds the allowable limit.
Positive or negative surge voltages entering via the input terminal 14 too can trigger latch-up of the CMOS. In general, the CMOS is provided with a voltage clamping circuit (not shown in FIG. 11) composed of diffused resistor and diffused diode, for the purpose of protecting the gate insulating layer from dielectric breakdown. The diffused regions of the voltage clamping circuit form pn junctions with the substrate, and these pn junctions form parasitic bipolar transistors. These parasitic bipolar transistors act and cause latch-up when an excessive surge is applied to the input terminal 14.
There are various measures for preventing latch-up. Typical examples are as follows:
(i) Prevention of external noise: Latch-up can be prevented by limiting the entry of external current noise into the device by the use of resistors or capacitors connected to the input or output terminal.
(ii) Prevention of the thyristor's turning on: The condition required to turn on the thyristor structure formed by the parasitic transistors Q.sub.3 and Q.sub.4 is given by Hfe.sub.3 .times.Hfe.sub.4 .gtoreq.1. Therefore, the thyristor is prevented from turning on by designing the CMOS structure such that Hfe.sub.3 .times.Hfe.sub.4 becomes smaller than one.
(iii) Limitation of current: In this measure, the current through the thyristor is limited below a holding current which is the minimum current required to maintain the thyristor in the on state after it is triggered into the on state.
(iv) Reduction of base resistances: Reduction of the base resistances Rn.sub.3 and Rp of the transistors Q.sub.3 and Q.sub.4 causes reduction of the voltage drops developed across the resistances. Therefore, it becomes more difficult for the transistors Q.sub.3 and Q.sub.4 to turn on.
Among these measures, (i) and (iii) impose restraints on the output current and operating speed of the CMOS inverter. Therefore, the measures (ii) and (iv) are employed widely.
One conventional example is shown in FIGS. 13 and 14. The CMOS structure shown in FIG. 13 is almost the same as the CMOS structure of FIG. 11, but different in the following points. In the structure of FIG. 13, the distance d between the pMOS 13, and the p well 2 is increased to a value equal to or greater than about 200 micrometers. Therefore, in each of the parasitic pnp transistors Q.sub.1 and Q.sub.3, the base width is increased, and accordingly, the current gain Hfe is decreased. Furthermore, an n.sup.+ -type substrate contact region 18 is formed in the n substrate 1 between the pMOS 13 and the nMOS 7, and a p.sup.+ -type well contact region 19 is formed in the p well 2 so as to surround the nMOS 7. With the contact regions 18 and 19, the base resistances Rn.sub.1, Rn.sub.3 and Rp of the parasitic transistors Q.sub.1, Q.sub.3 and Q.sub.4 are reduced.
In this device, the p well region 2 is spaced far from the drain region 9. Therefore, most of the holes which are injected from the drain region 9 into the n substrate 1 because of the positive surge voltage applied to the output terminal 15, recombine with electrons and disappear in the n substrate 1. It is only a fraction of the injected holes which can flow into the p well region 2 as the collector current Ic.sub.1 of the transistor Q.sub.1, and flow out through the base resistance Rp into the low potential terminal 17.
Furthermore, the base resistance Rp is reduced by the p.sup.+ well contact region 19. As a result, the voltage drop Ic.sub.1 .times.Rp is small, and the transistor Q.sub.4 hardly turns on.
If the collector current Ic.sub.1 increases, and the transistor Q.sub.4 is turned on because of an increase of the voltage drop Ic.sub.1 .times.Rp, the collector current Ic.sub.4 is supplied mostly from the substrate contact region 18, and the collector current Ic.sub.4 coming from the substrate contact region 12 adjacent the source region 8 is very small.
The base resistance Rn.sub.3 is reduced by the path of the n.sup.+ substrate contract region 18. Therefore, the transistor Q.sub.4 is hardly turned on even if the collector current Ic.sub.4 flows therethrough.
With this structure which makes it difficult for the parasitic thyristor to turn on, the CMOS device of FIG. 13 is improved in withstanding latch-up.
However, the CMOS device of FIG. 13 is disadvantageous in that the chip size and the fabricating cost are increased by the necessity for increasing the distance d between the pMOS 13 and the p well 2 beyond 200 micrometers.
FIGS. 15 and 16 show another conventional CMOS device. The CMOS structure of FIG. 15 is the same as that of FIG. 13 except that the device of FIG. 15 is further provided with a p-type hole collector region 21 in the n substrate 1 between the pMOS 13 and the n.sup.+ substrate contact region 18. The hole collector region 21 is connected with the low potential terminal 17 of Vss, and therefore, serves as a collector of the pnp transistor Q.sub.1, as shown in FIG. 16.
When a positive surge equal to or greater than Vdd enters the device from the output terminal, the hole collector region 21 collects the holes injected from the drain region 9 of the pMOS 13 into the n substrate 1, and leads them to the low potential point of Vss. By so doing, the hole collector region 21 reduces the collector current Ic.sub.1 of the transistor Q.sub.1 flowing into the p well region 2 to a very low value.
In the CMOS structure of FIG. 15, the capability of withstanding latch-up is improved with the hole collector region 21 instead of increasing the distance d between the pMOS 13 and the p well 2, and hence without the necessity of increasing the chip size too much.
However, the CMOS structure of FIG. 15 requires not only the hole collector region 21, but also a metal lead connecting the hole collector region 21 to the low potential Vss, and a metal lead connecting the substrate contact region 18 to the supply voltage Vdd both of which must be formed on the top side of the semiconductor substrate 1. Therefore, the actual layout is considerably complicated, and reduction in chip size is not so easy.
Recently, there has been proposed a MOS device having a Schottky source-drain structure. This structure eliminates the possibility of injection of the minority carriers at least in principle, so that the device is more resistant to latch-up. However, this structure introduces an undesired offset voltage, and decreases the transconductance gm by increasing the source resistance.